//=====================================================================
//    COPYRIGHT(C) Innobeam
//    ALL RIGHTS RESERVED
//=====================================================================
//Filename    : packRGS.v rev 1.0
//Created On  : 2019-10-11
//Author      : fei.yu
//Description : package the TX words to lan9252 to EtherCAT bus
//Include     : 
//Modification: fei.yu
//=====================================================================
module pack_BFH (		
			iClk			,	//
			iRst_n			,	//reset in low active
			//connect to lan9252 module
			iDpram_Ren,			//input read enable,from lan9252 module
			ovDpram_data,		//output 32bit data to be written to lan9252 module
			ivDpram_addr,		//input 4bit PRAM address from lan9252 module
			//from data_operation module
			ivBSC_Key_1,			//input 16bit 
			ivBSC_Wheel1_1,				//input	16bit 
			ivBSC_Wheel2_1,				//input	16bit 
			ivBSC_Wheel3_1,				//input	16bit 
			ivBSC_VERSION_1,				//input	16bit 
			ivBSC_Key_2,			//input 16bit 
			ivBSC_Wheel1_2,				//input	16bit 
			ivBSC_Wheel2_2,				//input	16bit 
			ivBSC_Wheel3_2,				//input	16bit 
			ivBSC_VERSION_2,				//input	16bit 
			ivHHC_Key_1,			//input 16bit 
			ivHHC_Wheel1_1,				//input	16bit 
			ivHHC_Wheel2_1,				//input	16bit 
			ivHHC_Wheel3_1,				//input	16bit 
			ivHHC_VERSION_1,				//input	16bit 
			ivHHC_Key_2,			//input 16bit 
			ivHHC_Wheel1_2,				//input	16bit 
			ivHHC_Wheel2_2,				//input	16bit 
			ivHHC_Wheel3_2,				//input	16bit 
			ivHHC_VERSION_2,			//input	16bit 	
			ivHBC_LinkState		
			);
//========================================================================
//    parameter
//========================================================================

//========================================================================
//    port
//========================================================================
input							iClk;
input							iRst_n;

output			[31:0]			ovDpram_data;
input			[9:0]			ivDpram_addr;
input							iDpram_Ren;

input			[15:0]			ivBSC_Key_1;
input			[15:0]			ivBSC_Wheel1_1;
input			[15:0]			ivBSC_Wheel2_1;
input			[15:0]			ivBSC_Wheel3_1;
input			[31:0]			ivBSC_VERSION_1;
input			[15:0]			ivBSC_Key_2;
input			[15:0]			ivBSC_Wheel1_2;
input			[15:0]			ivBSC_Wheel2_2;
input			[15:0]			ivBSC_Wheel3_2;
input			[31:0]			ivBSC_VERSION_2;
		
input			[15:0]			ivHHC_Key_1;
input			[15:0]			ivHHC_Wheel1_1;
input			[15:0]			ivHHC_Wheel2_1;
input			[15:0]			ivHHC_Wheel3_1;
input			[15:0]			ivHHC_VERSION_1;
input			[31:0]			ivHHC_Key_2;
input			[15:0]			ivHHC_Wheel1_2;
input			[15:0]			ivHHC_Wheel2_2;
input			[15:0]			ivHHC_Wheel3_2;
input			[31:0]			ivHHC_VERSION_2;
input  			[15:0]			ivHBC_LinkState;
		
//========================================================================
//    signal
//========================================================================					
reg				[31:0]			rvDpram_data;

assign ovDpram_data = rvDpram_data;
//decode address and output data buffer to lan9252
always @(posedge iClk or negedge iRst_n)begin
if(iRst_n == 1'b0)begin
	rvDpram_data <= 32'd0;
	end
else begin
	if(iDpram_Ren == 1'b1)begin
		case(ivDpram_addr)
		4'd0:begin
			rvDpram_data <= {ivBSC_Wheel1_1,ivBSC_Key_1};
			end
		4'd1:begin
			rvDpram_data <= {ivBSC_Wheel3_1,ivBSC_Wheel2_1};
			end
		4'd2:begin
			rvDpram_data <= ivBSC_VERSION_1;
			end
		4'd3:begin
			rvDpram_data <= {ivBSC_Wheel1_2,ivBSC_Key_2};
			end
		4'd4:begin
			rvDpram_data <= {ivBSC_Wheel3_2,ivBSC_Wheel2_2};
			end
		4'd5:begin
			rvDpram_data <= ivBSC_VERSION_2;
			end
		4'd6:begin
			rvDpram_data <= {ivHHC_Wheel1_1,ivHHC_Key_1};
			end
		4'd7:begin
			rvDpram_data <= {ivHHC_Wheel3_1,ivHHC_Wheel2_1};
			end
		4'd8:begin
			rvDpram_data <= ivHHC_VERSION_1;
			end
		4'd9:begin
			rvDpram_data <= {ivHHC_Wheel1_2,ivHHC_Key_2};
			end
		4'd10:begin
			rvDpram_data <= {ivHHC_Wheel3_2,ivHHC_Wheel2_2};
			end
		4'd11:begin
			rvDpram_data <= ivHHC_VERSION_2;
			end
		default:begin
			rvDpram_data <= {16'hFF,16'h00};
			end
		endcase
		end
	else begin
		rvDpram_data <= rvDpram_data;
		end
	end
end
endmodule

